Job Number: z5G7h3l6a1kMvyS65NP3c1xWEY7_rW0IpwGaoYH3pnE=
Pay Rate: 84-94 Hourly USD
Job Role: Design Verification Engineer (Leadership/Management Experience)
Job Location: Mountain View, CA
Job Type: Contract
- 8+ years of ASIC verification experience.
- Experience in System Verilog testbench development and UVM methodology is a must.
- Must have hands-on experience with at least 2 SoC/Sub-System/IP verification projects, along with SV.
- UVM based testbench development for at least 3 year.
- Hands-on experience on CPU(s) based SoC verification and writing/maintaining C-SV tests.
- Hands-on experience with UVM/OVM and System Verilog through development of test bench.
- components, generating directed and random stimulus, and coding cover points and assertions.
- Experience in developing test and coverage plan, Verification environment and validation plan.
- Experience in debugging design and driving coverage closure.
- Experience in verification of AMBA protocols and one of the protocols like PCIe/HBM/DDR.
- Knowledge of and basic working experience on C/C++ and Python based script.
- Experience in Gate Level Simulation, Pre/Post Silicon Validation support.
- Experience in leading team of 5-10 engineers for at least 2 years.
- Experience in scope estimation, schedule definition, work closely with team for tracking.
- Experience in working with customer and team leads for measuring schedule/quality matrices.
- Excellent communication skills and demonstrate the desire to take on diverse challenges.
Roles and responsibilities
- Be part of a team working on verification of complex IPs and sub-systems that are part of modern SoCs.
- Act as an effective communication bridge between Client Leads and India Offshore Team. Represent.
- Offshore Team effectively w.r.t status and issue communication.
- Work with Team lead to review schedule and quality of deliverable from team and ensure KPIs of the program are met.
- Work on individual assignments as defined by customer.
- Minimum BS (EE or CS) required with 8+ years of relevant experience.